User story #892: Test FLS v0.2.0 against FLS v0.2.0 test bench - Fast Logic Solver Test-bench - F4E-CODAC - redmine

User story #892

Test FLS v0.2.0 against FLS v0.2.0 test bench

Added by Katarina Cindric almost 4 years ago. Updated over 3 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Katarina Cindric

Target version:

Test bench for FLS v0.2.0

Start date:

29.06.2021

Due date:

% Done:

Estimated time:

Git branch (link):

Git merge to develop (link):

SVN commit (link/?p=rev):

Description

Test FLS v0.2.0 against FLS v0.2.0 test bench

History

#1 Updated by Katarina Cindric almost 4 years ago

Status changed from New to Arch: Rev

#2 Updated by Pedro Lourenco almost 4 years ago

Objective successfully achieved.

Tag v0.2.0 - Issue detected - read operations on standard registers only allowed in STATE_CONFIG. It should be possible to read any register in any state, even in an STATE_ERROR. Requested a new minor release 'fls_0.2.1' to address this issue. Issue detecetd in fls_v0.1.0 has been succesfully corrected (tested under CONFIG state).

For further details Please see [[https://vcis-gitlab.f4e.europa.eu/plourenco/flstestbench/-/blob/master/README.md]].

Test results (https://vcis-gitlab.f4e.europa.eu/plourenco/flstestbench/-/blob/master/Software/MARTe2/Docs/Logs/FLSTestBench_Report_GTest_tag_fls_v0.2.0_2021-06-22_11:31:16.xml):

<?xml version="1.0" encoding="UTF-8"?>
<testsuites tests="175" failures="27" disabled="0" errors="0" timestamp="2021-06-22T11:31:00" time="4.255" name="AllTests">
  <testsuite name="FlsStateMachineGTest" tests="122" failures="27" disabled="0" errors="0" time="2.571">
    <testcase name="TestHelperConstructor" status="run" time="0" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_RC_INIT_SRBR_RC_SR1_RC_INIT_SRBR_RC" status="run" time="0.228" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_FORCEINPUT_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR1_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR2_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_R0_RC" status="run" time="0.012" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1179&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1179
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_R0_RC_WC" status="run" time="0.012" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1196&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1196
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_R0_WC" status="run" time="0.014" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_R0_WC_RC" status="run" time="0.015" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1230&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1230
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_INIT_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1247&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1247
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_INIT_R0_RC_WC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1264&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1264
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_INIT_R0_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_INIT_R0_WC_RC" status="run" time="0.023" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1298&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1298
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_CONFIG_R0_RC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_CONFIG_R0_RC_WC" status="run" time="0.026" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_CONFIG_R0_WC" status="run" time="0.023" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_CONFIG_R0_WC_RC" status="run" time="0.026" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_NORMALOP_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1383&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1383
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_NORMALOP_R0_RC_WC" status="run" time="0.019" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1400&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1400
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_NORMALOP_R0_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_NORMALOP_R0_WC_RC" status="run" time="0.022" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1434&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1434
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_BYPASS_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1451&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1451
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_BYPASS_R0_RC_WC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1468&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1468
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_BYPASS_R0_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_BYPASS_R0_WC_RC" status="run" time="0.023" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1502&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1502
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_FORCEINPUT_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1519&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1519
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_FORCEINPUT_R0_RC_WC" status="run" time="0.019" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1536&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1536
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_FORCEINPUT_R0_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_FORCEINPUT_R0_WC_RC" status="run" time="0.022" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1570&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1570
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR0_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1587&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1587
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR0_R0_RC_WC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1604&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1604
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR0_R0_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR0_R0_WC_RC" status="run" time="0.022" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1638&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1638
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR1_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1655&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1655
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR1_R0_RC_WC" status="run" time="0.019" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1672&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1672
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR1_R0_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR1_R0_WC_RC" status="run" time="0.022" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1706&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1706
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR2_R0_RC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1723&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1723
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR2_R0_RC_WC" status="run" time="0.02" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1740&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1740
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR2_R0_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR2_R0_WC_RC" status="run" time="0.023" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1774&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1774
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_SRBR_WC" status="run" time="0.014" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_INIT_SRBR_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_CONFIG_SRBR_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_NORMALOP_SRBR_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_BYPASS_SRBR_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_FORCEINPUT_SRBR_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR0_SRBR_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR1_SRBR_WC" status="run" time="0.021" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_STATE_ERROR2_SRBR_WC" status="run" time="0.022" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_R0_RC_CONFIG_R0_WC_RC_INIT_R0_RC" status="run" time="0.013" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1944&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1944
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_R0_WCRC_CONFIG_NORMALOP_CONFIG_INIT" status="run" time="0.031" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1961&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1961
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_R0_WCRC_CONFIG_TO_ERROR2" status="run" time="0.032" classname="FlsStateMachineGTest">
      <failure message="FlsStateMachineGTest.cpp:1978&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsStateMachineGTest.cpp:1978
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_INIT_PADDING" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_CONFIG_PADDING" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_NORMALOP_PADDING" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_BYPASS_PADDING" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_FORCEINPUT_PADDING" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_ERROR0_PADDING" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_ERROR1_PADDING" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_ERROR2_PADDING" status="run" time="0.018" classname="FlsStateMachineGTest" />
  </testsuite>
  <testsuite name="FlsRegisterManagerGTest" tests="25" failures="0" disabled="0" errors="0" time="0.447">
    <testcase name="TestHelperConstructor" status="run" time="0.001" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_StAddr" status="run" time="0.015" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_SetAddrInvalid" status="run" time="0.016" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdAddr" status="run" time="0.016" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdAddrInvalid" status="run" time="0.015" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_StInvalidRdAddr" status="run" time="0.017" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_StRdAddr" status="run" time="0.016" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_Wr" status="run" time="0.017" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_Rd" status="run" time="0.016" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrRd" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdWr" status="run" time="0.018" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrInc" status="run" time="0.017" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdInc" status="run" time="0.018" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrIncRdInc" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncWrInc" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrIncWr" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrIncRd" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrWrInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrRdInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncWr" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncRd" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdWrInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdRdInc" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_CmdsWithReplyBit_0x0000" status="run" time="0.025" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_CmdsWithReplyBit_0xF0F0" status="run" time="0.026" classname="FlsRegisterManagerGTest" />
  </testsuite>
  <testsuite name="FlsPlcInterfaceGTest" tests="28" failures="0" disabled="0" errors="0" time="1.237">
    <testcase name="TestHelperConstructor" status="run" time="0.001" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r" status="run" time="0.22" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r4r" status="run" time="0.013" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1w4r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4w4r4w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r3w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r2w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_3r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r2w1r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r1r1r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1m3r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r1m2r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r1m1r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_3r1m" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r1rp2r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5ms_4r" status="run" time="0.027" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5ms_4r4r" status="run" time="0.047" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl30ms_4r" status="run" time="0.102" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl39ms_4r" status="run" time="0.131" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl40ms_4r" status="run" time="0.132" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_10_10ms_4r" status="run" time="0.038" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl39_5_5ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl40_5_5ms_4r" status="run" time="0.062" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_39_5ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_40_5ms_4r" status="run" time="0.063" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_5_39ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_5_40ms_4r" status="run" time="0.062" classname="FlsPlcInterfaceGTest" />
  </testsuite>
</testsuites>

#3 Updated by Katarina Cindric over 3 years ago

Status changed from Arch: Rev to Unit: Rev

#4 Updated by Katarina Cindric over 3 years ago

Assignee changed from Pedro Lourenco to Katarina Cindric

#5 Updated by Katarina Cindric over 3 years ago

Status changed from Unit: Rev to Closed

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Fast Logic Solver Test-bench

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User story #892

Test FLS v0.2.0 against FLS v0.2.0 test bench

History

#1 Updated by Katarina Cindric almost 4 years ago

#2 Updated by Pedro Lourenco almost 4 years ago

#3 Updated by Katarina Cindric over 3 years ago

#4 Updated by Katarina Cindric over 3 years ago

#5 Updated by Katarina Cindric over 3 years ago