Katarina Cindric
- Registered on: 26.07.2019
- Last connection: 15.05.2024
Issues
- Assigned issues: 14
- Reported issues: 42
Projects
- MARTe2 (Developer, 08.01.2021)
- MARTe2-core (Manager, Developer, 08.01.2021)
- MARTe2-components (Manager, 08.04.2021)
- Fast Logic Solver Test-bench (Manager, Developer, 22.04.2021)
- RTDisplay (Developer, 24.11.2023)
Activity
30.11.2021
- 09:30 Fast Logic Solver Test-bench User story #813 (Arch: Rev): Test pulse/probe in ISE in loopback mode
- 09:30 Fast Logic Solver Test-bench User story #984 (Arch: Rev): Test PLC interface v0.3.0
- 09:30 Fast Logic Solver Test-bench User story #984 (Arch: Rev): Test PLC interface v0.3.0
- Test PLC interface v0.3.0 - CRC validation
- 09:27 Fast Logic Solver Test-bench User story #975 (Unit: Rev): Test FC interface v0.1.0 with FC test-bench
- 09:27 Fast Logic Solver Test-bench User story #974 (Unit: Rev): Develop FC interface test bench v0.1.0
- 09:27 Fast Logic Solver Test-bench User story #971 (Unit: Rev): Test FLS v0.8.0 against FLS v0.8.0 test bench
- 09:27 Fast Logic Solver Test-bench User story #972 (Unit: Rev): Develop FLS v0.9.0 test bench
- 09:27 Fast Logic Solver Test-bench User story #973 (Unit: Rev): Test FLS v0.9.0 against FLS v0.9.0 test bench
- 09:27 Fast Logic Solver Test-bench User story #970 (Unit: Rev): Develop FLS v0.8.0 test bench
- 09:26 Fast Logic Solver Test-bench User story #815 (Unit: Rev): Migrate signal generator to Labview
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