User story #903: Test FLS v0.3.1 against FLS v0.3.0 test bench - Fast Logic Solver Test-bench - F4E-CODAC - redmine

User story #903

Test FLS v0.3.1 against FLS v0.3.0 test bench

Added by Katarina Cindric over 3 years ago. Updated over 3 years ago.

Status:

Closed

Priority:

Normal

Assignee:

Pedro Lourenco

Target version:

Test bench for FLS v0.3.0

Start date:

13.07.2021

Due date:

% Done:

Estimated time:

Git branch (link):

Git merge to develop (link):

SVN commit (link/?p=rev):

Description

Main changes:
- only command "set address" used to set both read/write addresses

Software_MARTe2_Docs_Logs_FLSTestBench_Report_GTest_tag_fls_v0.3.1_2021-07-14_14_57_41.xml (46.7 KB) Software_MARTe2_Docs_Logs_FLSTestBench_Report_GTest_tag_fls_v0.3.1_2021-07-14_14_57_41.xml	GTests report XML file.	Pedro Lourenco, 14.07.2021 17:09
Software_MARTe2_Docs_Logs_FLSTestBench_Report_Coverage_tag_fls_v0.3.1_2021-07-14_14_57_41.log (1.55 KB) Software_MARTe2_Docs_Logs_FLSTestBench_Report_Coverage_tag_fls_v0.3.1_2021-07-14_14_57_41.log	Coverage report GTest file.	Pedro Lourenco, 14.07.2021 17:10

History

#1 Updated by Katarina Cindric over 3 years ago

Status changed from New to Arch: Rev

#2 Updated by Pedro Lourenco over 3 years ago

FLS tag 'fls_v0.3.1' successfully tested using FLSTestBench v0.3.0.

Test result report: Issue detected - The implementation of the Set Address (code 0x0) and Readback Address (code 0x1) commands, replacing the previous Set Write Address and Set Read Address, has been successfully implemented & tested. The correction of issue (ii) in the previous release enabled to compile firmware T3. However, it also resulted in missing addresses for FW configurations T0 and T4. Please see documentation for further details. ([[https://vcis-gitlab.f4e.europa.eu/plourenco/flstestbench/-/tree/fls_v0.3.1]]).

These issues shall be corrected in the next release fls_v0.3.2.

Integration Tests (GTest) XML report (log also in attachment):

<?xml version="1.0" encoding="UTF-8"?>
<testsuites tests="287" failures="42" disabled="0" errors="0" timestamp="2021-07-14T14:56:30" time="39.04" name="AllTests">
  <testsuite name="FlsStateMachineGTest" tests="122" failures="0" disabled="0" errors="0" time="2.837">
    <testcase name="TestHelperConstructor" status="run" time="0.001" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_RC_INIT_SRBR_RC_SR1_RC_INIT_SRBR_RC" status="run" time="0.227" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_INIT_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_CONFIG_SRBR_RC_SR1_WC_ERROR1_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_ERROR0_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_NORMALOP_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_INIT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_CONFIG_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_BYPASS_SRBR_RC_SR1_WC_FORCEINPUT_SRBR_RC" status="run" time="0.018" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_NORMALOP_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_BYPASS_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_WC_ERROR0_SRBR_RC_SR1_WC_ERROR2_SRBR_RC" status="run" time="0.019" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_STATE_DEFAULT_R0_RC" status="run" time="0.016" classname="FlsStateMachineGTest" />
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    <testcase name="TestStateMachine_SequenceCheck_SR0_SR1_ERROR2_PADDING" status="run" time="0.018" classname="FlsStateMachineGTest" />
  </testsuite>
  <testsuite name="FlsRegisterManagerGTest" tests="25" failures="0" disabled="0" errors="0" time="0.449">
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    <testcase name="TestRegisterLoop_Addr0_WrIncRdInc" status="run" time="0.021" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncWrInc" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrIncWr" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrIncRd" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrWrInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_WrRdInc" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncWr" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdIncRd" status="run" time="0.02" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdWrInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_RdRdInc" status="run" time="0.019" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_CmdsWithReplyBit_0x0000" status="run" time="0.026" classname="FlsRegisterManagerGTest" />
    <testcase name="TestRegisterLoop_Addr0_CmdsWithReplyBit_0xF0F0" status="run" time="0.026" classname="FlsRegisterManagerGTest" />
  </testsuite>
  <testsuite name="FlsRegisterMapGTest" tests="112" failures="42" disabled="0" errors="0" time="34.513">
    <testcase name="TestHelperConstructor" status="run" time="0.001" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_RD_CK_ALL_T0" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:63&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:63
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_DEFAULT_WR_CK_ALL_T0" status="run" time="0.363" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_RDINC_CK_ALL_T0" status="run" time="0.055" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:97&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:97
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_DEFAULT_WRINC_CK_ALL_T0" status="run" time="0.145" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RD_CK_ALL_T0" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:131&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:131
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_INIT_WR_CK_ALL_T0" status="run" time="0.356" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RDINC_CK_ALL_T0" status="run" time="0.055" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:165&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:165
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_INIT_WRINC_CK_ALL_T0" status="run" time="0.144" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_RD_CK_ALL_T0" status="run" time="0.129" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:199&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:199
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_WR_CK_ALL_T0" status="run" time="0.128" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:216&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:216
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_RDINC_CK_ALL_T0" status="run" time="0.089" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:233&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:233
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_WRINC_CK_ALL_T0" status="run" time="0.088" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:250&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:250
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_RD_CK_ALL_T0" status="run" time="0.128" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:267&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:267
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_WR_CK_ALL_T0" status="run" time="0.609" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_RDINC_CK_ALL_T0" status="run" time="0.089" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:301&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:301
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_WRINC_CK_ALL_T0" status="run" time="0.398" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RD_CK_ALL_T0" status="run" time="0.129" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:335&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:335
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_BYPASS_WR_CK_ALL_T0" status="run" time="0.609" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RDINC_CK_ALL_T0" status="run" time="0.088" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:369&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:369
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_BYPASS_WRINC_CK_ALL_T0" status="run" time="0.399" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RD_CK_ALL_T0" status="run" time="0.128" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:403&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:403
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_FORCEINPUT_WR_CK_ALL_T0" status="run" time="0.61" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RDINC_CK_ALL_T0" status="run" time="0.089" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:437&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:437
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_FORCEINPUT_WRINC_CK_ALL_T0" status="run" time="0.398" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RD_CK_ALL_T0" status="run" time="0.128" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:471&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:471
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR0_WR_CK_ALL_T0" status="run" time="0.61" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RDINC_CK_ALL_T0" status="run" time="0.089" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:505&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:505
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR0_WRINC_CK_ALL_T0" status="run" time="0.398" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RD_CK_ALL_T0" status="run" time="0.129" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:539&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:539
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR1_WR_CK_ALL_T0" status="run" time="0.609" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RDINC_CK_ALL_T0" status="run" time="0.089" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:573&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:573
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR1_WRINC_CK_ALL_T0" status="run" time="0.398" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RD_CK_ALL_T0" status="run" time="0.128" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:607&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:607
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR2_WR_CK_ALL_T0" status="run" time="0.61" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RDINC_CK_ALL_T0" status="run" time="0.088" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:641&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:641
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR2_WRINC_CK_ALL_T0" status="run" time="0.399" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_OPERATION_SEQUENCE_T0" status="run" time="0.094" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:675&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:675
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_DEFAULT_RD_CK_ALL_T3" status="run" time="0.552" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_WR_CK_ALL_T3" status="run" time="0.346" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_RDINC_CK_ALL_T3" status="run" time="0.127" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_WRINC_CK_ALL_T3" status="run" time="0.128" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RD_CK_ALL_T3" status="run" time="0.344" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_WR_CK_ALL_T3" status="run" time="0.346" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RDINC_CK_ALL_T3" status="run" time="0.127" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_WRINC_CK_ALL_T3" status="run" time="0.128" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_RD_CK_ALL_T3" status="run" time="0.567" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_WR_CK_ALL_T3" status="run" time="0.567" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_RDINC_CK_ALL_T3" status="run" time="0.35" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_WRINC_CK_ALL_T3" status="run" time="0.349" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_RD_CK_ALL_T3" status="run" time="0.568" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_WR_CK_ALL_T3" status="run" time="0.569" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_RDINC_CK_ALL_T3" status="run" time="0.349" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_WRINC_CK_ALL_T3" status="run" time="0.35" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RD_CK_ALL_T3" status="run" time="0.568" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_WR_CK_ALL_T3" status="run" time="0.569" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RDINC_CK_ALL_T3" status="run" time="0.349" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_WRINC_CK_ALL_T3" status="run" time="0.351" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RD_CK_ALL_T3" status="run" time="0.567" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_WR_CK_ALL_T3" status="run" time="0.568" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RDINC_CK_ALL_T3" status="run" time="0.349" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_WRINC_CK_ALL_T3" status="run" time="0.351" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RD_CK_ALL_T3" status="run" time="0.567" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_WR_CK_ALL_T3" status="run" time="0.563" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RDINC_CK_ALL_T3" status="run" time="0.346" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_WRINC_CK_ALL_T3" status="run" time="0.347" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RD_CK_ALL_T3" status="run" time="0.562" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_WR_CK_ALL_T3" status="run" time="0.564" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RDINC_CK_ALL_T3" status="run" time="0.346" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_WRINC_CK_ALL_T3" status="run" time="0.347" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RD_CK_ALL_T3" status="run" time="0.563" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_WR_CK_ALL_T3" status="run" time="0.563" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RDINC_CK_ALL_T3" status="run" time="0.346" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_WRINC_CK_ALL_T3" status="run" time="0.347" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_OPERATION_SEQUENCE_T3" status="run" time="0.8" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_RD_CK_ALL_T4" status="run" time="0.325" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1321&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1321
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_DEFAULT_WR_CK_ALL_T4" status="run" time="0.37" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_DEFAULT_RDINC_CK_ALL_T4" status="run" time="0.063" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1355&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1355
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_DEFAULT_WRINC_CK_ALL_T4" status="run" time="0.157" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RD_CK_ALL_T4" status="run" time="0.117" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1389&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1389
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_INIT_WR_CK_ALL_T4" status="run" time="0.37" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_INIT_RDINC_CK_ALL_T4" status="run" time="0.062" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1423&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1423
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_INIT_WRINC_CK_ALL_T4" status="run" time="0.157" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_CONFIG_RD_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1457&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1457
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_WR_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1474&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1474
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_RDINC_CK_ALL_T4" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1491&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1491
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_CONFIG_WRINC_CK_ALL_T4" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1508&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1508
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_RD_CK_ALL_T4" status="run" time="0.151" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1525&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1525
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_WR_CK_ALL_T4" status="run" time="0.601" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_NORMALOP_RDINC_CK_ALL_T4" status="run" time="0.096" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1559&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1559
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_NORMALOP_WRINC_CK_ALL_T4" status="run" time="0.389" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RD_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1593&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1593
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_BYPASS_WR_CK_ALL_T4" status="run" time="0.601" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_BYPASS_RDINC_CK_ALL_T4" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1627&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1627
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_BYPASS_WRINC_CK_ALL_T4" status="run" time="0.389" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RD_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1661&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1661
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_FORCEINPUT_WR_CK_ALL_T4" status="run" time="0.602" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_FORCEINPUT_RDINC_CK_ALL_T4" status="run" time="0.096" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1695&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1695
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_FORCEINPUT_WRINC_CK_ALL_T4" status="run" time="0.388" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RD_CK_ALL_T4" status="run" time="0.151" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1729&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1729
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR0_WR_CK_ALL_T4" status="run" time="0.602" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR0_RDINC_CK_ALL_T4" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1763&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1763
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR0_WRINC_CK_ALL_T4" status="run" time="0.389" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RD_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1797&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1797
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR1_WR_CK_ALL_T4" status="run" time="0.602" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR1_RDINC_CK_ALL_T4" status="run" time="0.095" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1831&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1831
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR1_WRINC_CK_ALL_T4" status="run" time="0.389" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RD_CK_ALL_T4" status="run" time="0.15" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1865&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1865
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR2_WR_CK_ALL_T4" status="run" time="0.601" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_ERROR2_RDINC_CK_ALL_T4" status="run" time="0.096" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1899&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1899
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
    <testcase name="TestRegisterMap_ERROR2_WRINC_CK_ALL_T4" status="run" time="0.388" classname="FlsRegisterMapGTest" />
    <testcase name="TestRegisterMap_OPERATION_SEQUENCE_T4" status="run" time="0.1" classname="FlsRegisterMapGTest">
      <failure message="FlsRegisterMapGTest.cpp:1933&#x0A;Value of: ret&#x0A;  Actual: false&#x0A;Expected: true" type=""><![CDATA[FlsRegisterMapGTest.cpp:1933
Value of: ret
  Actual: false
Expected: true]]></failure>
    </testcase>
  </testsuite>
  <testsuite name="FlsPlcInterfaceGTest" tests="28" failures="0" disabled="0" errors="0" time="1.24">
    <testcase name="TestHelperConstructor" status="run" time="0" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r" status="run" time="0.22" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r4r" status="run" time="0.013" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1w4r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4w4r4w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r3w" status="run" time="0.013" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r2w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_3r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_4r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r2w1r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r1r1r1w" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1m3r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_1r1m2r" status="run" time="0.013" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r1m1r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_3r1m" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl0ms_2r1rp2r" status="run" time="0.012" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5ms_4r" status="run" time="0.027" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5ms_4r4r" status="run" time="0.047" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl30ms_4r" status="run" time="0.102" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl39ms_4r" status="run" time="0.132" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl40ms_4r" status="run" time="0.132" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_10_10ms_4r" status="run" time="0.037" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl39_5_5ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl40_5_5ms_4r" status="run" time="0.063" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_39_5ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_40_5ms_4r" status="run" time="0.063" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_5_39ms_4r" status="run" time="0.061" classname="FlsPlcInterfaceGTest" />
    <testcase name="TestUartLoop_chdl5_5_40ms_4r" status="run" time="0.062" classname="FlsPlcInterfaceGTest" />
  </testsuite>
</testsuites>

#3 Updated by Katarina Cindric over 3 years ago

Status changed from Arch: Rev to Unit: Rev

#4 Updated by Katarina Cindric over 3 years ago

Status changed from Unit: Rev to Closed

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