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User story #813

Test pulse/probe in ISE in loopback mode

Added by Katarina Cindric almost 4 years ago. Updated over 3 years ago.

Status:
Arch: Rev
Priority:
Normal
Assignee:
-
Target version:
-
Start date:
22.04.2021
Due date:
% Done:

0%

Estimated time:
Git branch (link):
Git merge to develop (link):
SVN commit (link/?p=rev):

Description

Test pulse/probe in ISE in loopback mode

History

#1 Updated by Katarina Cindric almost 4 years ago

  • Assignee deleted (Pedro Lourenco)

#2 Updated by Katarina Cindric almost 4 years ago

  • Target version set to Test-bench for PLC interface v0.1.0

#3 Updated by Katarina Cindric almost 4 years ago

  • Status changed from New to Arch: Rev

#4 Updated by Katarina Cindric almost 4 years ago

  • Status changed from Arch: Rev to Code: Impl

#5 Updated by Katarina Cindric almost 4 years ago

  • Target version deleted (Test-bench for PLC interface v0.1.0)

#6 Updated by Katarina Cindric almost 4 years ago

  • Status changed from Code: Impl to New

#7 Updated by Katarina Cindric over 3 years ago

  • Status changed from New to Arch: Rev

#8 Updated by Pedro Lourenco over 3 years ago

Objective of testing the Pulse Generator and Pulse Probe components successfuly implemented. However, the two components were tested and validated individually with VHDL test benches oscilloscope measurements. For additional information see the following README.md files:

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