User story #904
Develop FLS v0.4.0 test bench
Start date:
13.07.2021
Due date:
% Done:
0%
Estimated time:
Git branch (link):
Git merge to develop (link):
SVN commit (link/?p=rev):
Description
Develop test-bench to test the FLS v0.4.0
History
#1 Updated by Katarina Cindric over 3 years ago
- Status changed from New to Arch: Rev
#2 Updated by Pedro Lourenco over 3 years ago
The FLSTestBench v0.4.x has been successfully implemented.
Key achievements (FLSInterface & FlsInputStage):- Integration and configuration of the Input Emulator (Pulse Generator VHDL) methods for integrated testing;
- Write/Read the registers relevant for fls_v0.4.x testing using bit fields instead of full 16bit registers as a single words;
- Deployed the initial set of 50 tests, targeting the basic requirements funtionalities of the Input Stage (and Clock Generator);
- Additional tests will be added once this basic set is marked/accepted as PASS.
The source code can be found on branch testbench_v04x : [[https://vcis-gitlab.f4e.europa.eu/plourenco/flstestbench/-/tree/testbench_v04x]]
#3 Updated by Katarina Cindric over 3 years ago
- Status changed from Arch: Rev to Unit: Rev
#4 Updated by Katarina Cindric over 3 years ago
- Assignee changed from Pedro Lourenco to Katarina Cindric