User story #808
Labview project with UART and probe/pulse and FIFOs
Status:
Closed
Priority:
Normal
Assignee:
Target version:
Start date:
22.04.2021
Due date:
% Done:
0%
Estimated time:
Git branch (link):
Git merge to develop (link):
SVN commit (link/?p=rev):
Description
Create Labview project with current versions of the UART, pulse and probe modules. Add the necessary 3 FIFOs and registers for configuration. The point of this exercise is to check usage
History
#1 Updated by Katarina Cindric almost 4 years ago
- Status changed from New to Code: Impl
#2 Updated by Katarina Cindric almost 4 years ago
- Target version set to Test-bench for PLC interface v0.1.0
#3 Updated by Katarina Cindric almost 4 years ago
- Status changed from Code: Impl to Closed
It was tested with 1 UART, 1 probe module, 1 pulse module and the FIFOs needed for MXI communication. Memory usage very low ~ 3%.