Fast Logic Solver Test-bench

22.04.2021

19:16 User story #811 (Code: Impl): Clean-up of probe vhdl code

Katarina Cindric

19:13 User story #811 (Closed): Clean-up of probe vhdl code

Clean-up of probe vhdl code Katarina Cindric

19:16 User story #810 (Code: Impl): Clean-up signal generator vhdl code

Katarina Cindric

19:13 User story #810 (Closed): Clean-up signal generator vhdl code

Clean-up signal generator vhdl code Katarina Cindric

19:16 User story #809 (Code: Impl): Clean-up UART module

Katarina Cindric

19:13 User story #809 (Closed): Clean-up UART module

Clean-up UART module Katarina Cindric

19:16 User story #808 (Code: Impl): Labview project with UART and probe/pulse and FIFOs

Katarina Cindric

19:12 User story #808 (Closed): Labview project with UART and probe/pulse and FIFOs

Create Labview project with current versions of the UART, pulse and probe modules. Add the necessary 3 FIFOs and regi... Katarina Cindric

19:16 User story #819 (Closed): Simple C app to test probe

Simple C app to test probe Katarina Cindric

19:16 User story #818 (Closed): Simple C app to test signal generator

Simple C app to test signal generator Katarina Cindric

19:15 User story #817 (Closed): Simple C app to test UART

Simple C app to test UART Katarina Cindric

19:15 User story #816 (Unit: Rev): Migrate probe to Labview

Migrate probe to Labview Katarina Cindric

19:15 User story #815 (Unit: Rev): Migrate signal generator to Labview

Migrate signal generator to Labview Katarina Cindric

19:14 User story #814 (Closed): Migrate UART to Labview

Migrate UART to Labview Katarina Cindric

19:14 User story #813 (Arch: Rev): Test pulse/probe in ISE in loopback mode

Test pulse/probe in ISE in loopback mode Katarina Cindric

19:14 User story #812 (Closed): Test UART in ISE in loop-back form

Test UART in ISE in loop-back form Katarina Cindric