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User story #812

Test UART in ISE in loop-back form

Added by Katarina Cindric almost 4 years ago. Updated almost 4 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Katarina Cindric
Target version:
Test-bench for PLC interface v0.1.0
Start date:
22.04.2021
Due date:
% Done:

0%

Estimated time:
Git branch (link):
Git merge to develop (link):
SVN commit (link/?p=rev):

Description

Test UART in ISE in loop-back form

History

#1 Updated by Katarina Cindric almost 4 years ago

  • Assignee deleted (Pedro Lourenco)

#2 Updated by Katarina Cindric almost 4 years ago

  • Target version set to Test-bench for PLC interface v0.1.0

#3 Updated by Katarina Cindric almost 4 years ago

  • Status changed from New to Code: Impl

#4 Updated by Katarina Cindric almost 4 years ago

  • Assignee set to Pedro Lourenco

#5 Updated by Katarina Cindric almost 4 years ago

  • Status changed from Code: Impl to Unit: Rev

#6 Updated by Pedro Lourenco almost 4 years ago

The UART module developed was successfully tested using VHDL test benches in ISE with ISIM. These are currently being migrated to VUNIT + ModelSim. The current UART version, also used in the LabView FPGA projects, can be found at [[https://vcis-gitlab.f4e.europa.eu/plourenco/flstestbench/-/blob/42694fba4bc84a3a823b0f58f65a51de38489125/Firmware/Xilinx/FLSTestBench/hdl/source/uart/lv_uart_wrapper.vhd]].

#7 Updated by Katarina Cindric almost 4 years ago

  • Assignee changed from Pedro Lourenco to Katarina Cindric

#8 Updated by Katarina Cindric almost 4 years ago

  • Status changed from Unit: Rev to Closed

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